54S301 Datasheet | Signetics

SiI-!nInnIet-lc'S TTL 256x1 RAM (54/74S200/201 TRI-STATE)554411~44SS220010 (54/74S301 OPEN COLLECTOR) I' 54/74S301 - - - - - - - - - - - - - - - - - F - E B - R - U A - R - Y - ' -97-S-i DIGITAL 8000 SERIES TTL/MEMORY DESCRIPTION The 54/74S200/201 and 54/74S301 are Schottky clamped TTL, read/write memory arrays organized as 256 words of one bit each. They feature either open collector or tri-state outputs options for optimization of word expansion in bussed organizations. Memory expansion is further enhanced by full on-chip address decoding, three chip enable inputs and PNP input transistors wh ich reduce input loading to 25IJA for a "1" level and -250IJA (S54S200/201/301) or -100IJA...