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SinootiCS 82S116 256-BIT BIPOLAR RAM (256xl RAM) 82S117 _;=_ .I _ _ _ _ _{_82S_11_6T_RI_-ST_AT_E>_{82_S1_17_0P_EN_CO_LL_EC_TOR---f}
FEBRUARY 1975
DIGITAL 8000 SERIES TTL/MEMORY
DESCRIPTION
The 82S116 and 82S117 are Schottky clamped TTL, read/write memory arrays organ ized as 256 words of one bit each. They feature either open collector or tri-state output options for optimization of word expansion in bussed organ izations. Memory expansion is fu rther enhanced by full on-chip address decoding, 3 chip enable inputs and PNP input transistors which reduce input loading to 25pA for a "1" level, and -1 ~OpA for a "0" level. During WRITE operation, the logical state of the output of both devices follows the complement of the data input being written.