Signetics 82S116
The 82S116 and 82S117 are Schottky clamped TTL, read/write memory arrays organ ized as 256 words of one bit each. They feature either open collector or tri-state output options for optimization of word expansion in bussed organ izations. This feature allows faster execution of WRITE-R EAD cycles, enhancing the performance of systems utilizing indirect addressing modes, and/or requiring immediate verification following a WRITE cycle.| Part No. | 82S116 |
|---|---|
| Datasheet | 82S116 Download |
| Manufacturer |  Signetics |
| Description | 256-BIT BIPOLAR RAM |
| Buy | Stock & Price |
DESCRIPTION
Memory expansion is fu rther enhanced by full on-chip address decoding, 3 chip enable inputs and PNP input transistors which reduce input loading to 25pA for a "1" level, and -1 ~OpA for a "0" level. During WRITE operation, the logical state of the output of both devices follows the complement of the data input being written. Both devices have fast read access and write cycle times, and thus are ideally su ited in high-speed memory applications such as "Cache", buffers, scratch pads, writable control stores, etc. Both 82S 116 and 82S 117 devices are available in the commercial temperature range. For the commercial temperature range, (OoC to +75°C) specify N82S116/117, B or F.FEATURES
● ORGANIZATION - 256 X 1● ADDRESS ACCESS TIME - 40n5, MAXIMUM
● WRITE CYCLE TIME - 25n5, MAXIMUM
● POWER DISSIPATION - 1.5mW/BIT TYPICAL
● INPUT LOADING - (-100JlA) MAXIMUM
● OUTPUT FOLLOWS COMPLEMENT OF DATA INPUT DURING WRITE
● ON-CHIP ADDRESS DECODING
● OUTPUT OPTION: TRI-STATE - 82S116 OP...
