82S116
DESCRIPTION
The 82S116 and 82S117 are Schottky clamped TTL, read/write memory arrays organ ized as 256 words of one bit each. They feature either open collector or tri-state output options for optimization of word expansion in bussed organ izations. Memory expansion is fu rther enhanced by full on-chip address decoding, 3 chip enable inputs and PNP input transistors which reduce input loading to 25p A for a "1" level, and -1 ~Op A for a "0" level. During WRITE operation, the logical state of the output of both devices follows the plement of the data input being written. This feature allows faster execution of WRITE-R EAD cycles, enhancing the performance of systems utilizing indirect addressing modes, and/or requiring immediate verification following a WRITE cycle. Both devices have fast read access and write cycle times, and thus are ideally su ited in high-speed memory applications such as "Cache", buffers, scratch pads, writable control stores, etc. Both 82S 116 and 82S 117 devices...
