82S116 Description
The 82S116 and 82S117 are Schottky clamped TTL, read/write memory arrays organ ized as 256 words of one bit each.
82S116 Key Features
- ORGANIZATION
- 256 X 1
- ADDRESS ACCESS TIME
- 40n5, MAXIMUM
- WRITE CYCLE TIME
- 25n5, MAXIMUM
- POWER DISSIPATION
- 1.5mW/BIT TYPICAL
- INPUT LOADING
- (-100JlA) MAXIMUM