DESCRIPTION
A D-type latch is used to enable the Tri-State output d ivers.1 n the TRANSPARENT READ mode, stored data is addressed by applying a binary code to the address inputs while holding STROBE high. In this mode the bit drivers will be controlled solely by CE1 and CE2 lines. In the LATCHED READ mode, outputs are held in their previous state (1, 0, or high Z) as long as STROB E is low, regard less of the state of address or ch ip enable. A positive STROBE transition causes data from the applied address to reach the outputs if the chip is enabled, and causes outputs to go to the high Z state if the chip is disabled. A negative STROBE transition causes outputs to be locked into their last Read Data cond ition if the chip was enabled, or causes outputs to be locked into the high Z condition if the chip was disabled. Both 82S214 and 82S215 devices are avai lable in the commercial and military temperature ranges. For the commercial temperature range (DoC to +75°C) specify N82S214/215 I.
Signetics
