SLGSSTVF16859V - DDR 13 to 26 Bit Registered Buffer

This page provides the datasheet information for the SLGSSTVF16859V, a member of the SLGSSTVF16859H DDR 13 to 26 Bit Registered Buffer family.

Product Overview

Silego

Part number	SLGSSTVF16859V
Manufacturer	Silego
File Size	336.09 KB
Description	DDR 13 to 26 Bit Registered Buffer
Datasheet	SLGSSTVF16859V Datasheet
Additional preview pages of the SLGSSTVF16859V datasheet.

The 14-bit SLGSSTVF16859 is a registered buffer designed for 2.3V to 2.7V VDD operating range.

Inputs are SSTL_2 levels, except for the LVCMOS RESET input.

Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signal (RESET).

Compatible with JEDEC standard SSTV16859.
Differential Clock inputs.
SSTL_2 data input signaling.
Supports SSTL_2 class I output specifications.
Output circuitry minimizes effects of SSO and unterminated lines www. DataSheet4U. com.
LVCMOS input levels on RESET pin.
2.3V-2.7V Operation for PC1600/2100/2700.
2.5V-2.7V Operation for PC3200.
Max Clock frequency > 210MHz Pin Configuration Q13A Q12A Q11A Q10A Q9A VDDQ G.

Other Datasheets by Silego

Published: Dec 18, 2008 |