SIS5503
Key Features
- Supports the 510\60, 567\66, 735\90, 815\100 MHz and 75 MHz Pentium Processor Supports M1 and Other Pentium Compatible CPU Supports the Pipelined Address Mode of the Pentium or the P54C Processor Integrated Second Level ( L2 ) Cache Controller - Write Through and Write Back Cache Modes - 8 bits or 7 bits Tag with Direct Mapped Organization - Supports Standard and Burst SRAMs - Supports 64 KBytes to 2 MBytes Cache Sizes - Cache Read/Write Cycle of 3-2-2-2 or 4-2-2-2 Using Standard SRAMs at 66 MHz - Cache Read/Write Cycle of 3-1-1-1 Using Burst SRAMs at 66 MHz
- Integrated DRAM Controller - Supports 8 Banks of SIMMs up to 512 MBytes of Cacheable Main Memory - Supports " Table- Free " DRAM Configuration - Concurrent Write Back - CAS#-before-RAS# Transparent DRAM Refresh - Supports 256K/512K/1M/2M/4M/16M xN 70ns Fast Page Mode and EDO DRAM - The Fastest Burst Cycle Speed for FP and EDO are 6-3-3-3 and 6-2-2-2 respectively - Programmable CAS# driving Current - Programmable DRAM Speed
- Two Programmable Non-Cacheable Regions
- Option to Disable Local Memory in Non-Cacheable Regions
- Shadow RAM in Increments of 16 KBytes
- Supports Pentium/P54C SMM Mode
- Supports CPU Stop Clock
- Provides High Performance PCI Arbiter - Supports Four PCI Masters - Supports Rotating Priority Mechanism - Hidden Arbitration Scheme Minimizes Arbitration Overhead
- 208-Pin PQFP Package
- 0.6µm CMOS Technology Preliminary V2.0 April 2, 1995 2 Silicon Integrated Systems Corporation SiS5501 PCI/ISA Cache Memory Controller
