C8051F230 Datasheet | Silicon Labs

25 MIPS, 8 kB Flash, 48-Pin Mixed-Signal MCU Analog Peripherals Two parators High-Speed 8051 µC Core - - Programmable hysteresis Configurable to generate interrupts or reset VDD Monitor and Brown-out Detector Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler; up to 21 interrupt sources 256 bytes data RAM 8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are reserved) 32 port I/O; all are 5 V tolerant Hardware SPI™ and UART serial ports available concurrently 3 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional...