Datasheet4U Logo Datasheet4U.com

CY2SSTV857-27 - Differential Clock Buffer/Driver DDR333/PC2700-Compliant

General Description

The CY2SSTV857-27 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications.

The CY2SSTV857-27 generates ten differential pair clock outputs from one differential pair clock input.

Key Features

  • Operating frequency: 60 MHz to 200 MHz.
  • Supports 266, 333 MHz DDR SDRAM.
  • 10 differential outputs from 1 differential input.
  • Spread-Spectrum-compatible.
  • Low jitter (cycle-to-cycle): < 75.
  • Very low skew: < 100 ps.
  • Power management control input.
  • High-impedance outputs when input clock < 10 MHz.
  • 2.5V operation.
  • Pin-compatible with CDC857-2 and -3.
  • 48-pin TSSOP package.
  • Industrial temp. of.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY2SSTV857-27 Differential Clock Buffer/Driver DDR333/PC2700-Compliant Cypress Semiconductor
CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant Cypress Semiconductor
CY2SSTV8575 Differential Clock Buffer/Driver Cypress Semiconductor
CY2SSTV850 Differential Clock Buffer/Driver Cypress Semiconductor
CY2SSTV855 Differential Clock Buffer/Driver Cypress Semiconductor

Other Datasheets by Silicon Laboratories

Part Number Description
CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant
CY2SSTV850 Differential Clock Buffer/Driver
CY2SSTV855 Differential Clock Buffer/Driver
CY28346-2 Clock Synthesizer
CY28354-400 210MHz 24 Output Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY2SSTV857-27 Differential Clock Buffer/Driver DDR333/PC2700-Compliant Features • Operating frequency: 60 MHz to 200 MHz • Supports 266, 333 MHz DDR SDRAM • 10 differential outputs from 1 differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps • Power management control input • High-impedance outputs when input clock < 10 MHz • 2.5V operation • Pin-compatible with CDC857-2 and -3 • 48-pin TSSOP package • Industrial temp. of –40° to +85°C • Conforms to JEDEC DDR specification Description The CY2SSTV857-27 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications.