CY2SSTV857-32 Datasheet PDF - Silicon Laboratories Differential Clock Buffer/Driver DDR400/PC3200-Compliant Specs

CY2SSTV857-32 - Differential Clock Buffer/Driver DDR400/PC3200-Compliant

Datasheet Summary

Description

The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications.

The CY2SSTV857-32 generates ten differential pair clock outputs from one differential pair clock input.

Features

Operating frequency: 60 MHz to 230 MHz.
Supports 400 MHz DDR SDRAM.
10 differential outputs from one differential input.
Spread-Spectrum-compatible.
Low jitter (cycle-to-cycle): < 75.
Very low skew: < 100 ps.
Power management control input.
High-impedance outputs when input clock < 20 MHz.
2.6V operation.
Pin-compatible with CDC857-2 and -3.
48-pin TSSOP and 40 QFN package.
Industrial tem.

Datasheet Details

Part number	CY2SSTV857-32
Manufacturer	Silicon Laboratories
File Size	80.88 KB
Description	Differential Clock Buffer/Driver DDR400/PC3200-Compliant
Datasheet	CY2SSTV857-32 Datasheet
Additional preview pages of the CY2SSTV857-32 datasheet.

📁 Similar Datasheet

CY2SSTV857-32 - Differential Clock Buffer/Driver DDR400/PC3200-Compliant (Cypress Semiconductor)

CY2SSTV857-27 - Differential Clock Buffer/Driver DDR333/PC2700-Compliant (Cypress Semiconductor)

CY2SSTV8575 - Differential Clock Buffer/Driver (Cypress Semiconductor)

CY2SSTV850 - Differential Clock Buffer/Driver (Cypress Semiconductor)

CY2SSTV855 - Differential Clock Buffer/Driver (Cypress Semiconductor)

CY2SSTV16857 - 14-Bit Regstered Buffer (SpectraLinear)

CY2SSTV16857 - 14-Bit Registered Buffer (Cypress Semiconductor)

CY2SSTV16859 - 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant (Cypress Semiconductor)

CY2SSTV16859 - 13-Bit to 26-Bit Registered Buffer (SpectraLinear)

CY2SSTU877 - 10-Output JEDEC-Compliant Zero Delay Buffer (Cypress Semiconductor)

Full PDF Text Transcription

Click to expand full text

CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant Features • Operating frequency: 60 MHz to 230 MHz • Supports 400 MHz DDR SDRAM • 10 differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps • Power management control input • High-impedance outputs when input clock < 20 MHz • 2.6V operation • Pin-compatible with CDC857-2 and -3 • 48-pin TSSOP and 40 QFN package • Industrial temperature of –40°C to 85°C • Conforms to JEDEC DDR specification Description The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications.

Published: Aug 4, 2018 |