SI514 Datasheet | Silicon Labs

Features - Programmable to any frequency - On-chip LDO for power supply from 100 k Hz to 250 MHz noise filtering - 0.026 ppb frequency tuning - 3.3, 2.5, or 1.8 V operation resolution - Differential (LVPECL, LVDS, - Glitch suppression on OE, power HCSL) or CMOS output options on and frequency transitions - Optional integrated 1:2 CMOS - Low jitter operation fanout buffer - 2- to 4-week lead times - Industry standard 5 x 7 and - Total stability includes 10-year 3.2 x 5 mm packages aging - - 40 to 85 o C operation - prehensive production test coverage includes crystal ESR and Applications - All-digital PLLs - DAC+ VCXO replacement - SONET/SDH/OTN - 3G-SDI/HD-SDI/SDI - Data - Industrial automation - FPGA/ASIC clock generation - FPGA synchronization Description The Si514 user-programmable I2C XO utilizes Silicon Laboratories' advanced PLL technology to provide any frequency from 100 k Hz to 250 MHz with programming resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this range using simple I2C mands. Ultra-fine tuning resolution replaces DACs and VCXOs with an all-digital PLL solution that improves performance where synchronization is necessary or in free-running reference clock applications. This solution provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested to guarantee performance and enhance reliability. The Si514 is factory-configurable for a wide variety of user specifications, including startup frequency, I2C address, supply voltage, output format, and stability. Specific configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators. Functional Block Diagram Si5602 Ordering Information: See page 28. Pin...