SI53019-A01A Datasheet | Silicon Labs

19-OUTPUT PCIE GEN 3 BUFFER Features - Nineteen 0.7 V current-mode, - Spread spectrum tolerable HCSL PCIe Gen 3 outputs - 50 ps output-to-output skew - 100 MHz /133 MHz PLL operation, supports PCIe and QPI - Fixed 0 ps input to output delay - Low phase jitter (Intel QPI, PCIe Gen 1/Gen 2/Gen 3/Gen 4 - PLL bandwidth SW SMBUS mon clock pliant - - programming overrides the latch value from HW pin 9 selectable SMBus addresses Fixed external feedback path - - - Gen 3 SRNS pliant 100 ps input-to-output delay Extended Temperature: - 40 to 85 °C - 8 dedicated OE pin - PLL or bypass mode - Package: 72-pin QFN Ordering Information: See page 32. Applications -...