SI53345 Datasheet | Silicon Labs

feature typical ultra-low jitter of 50 fs and operate over a wide frequency range from dc to 1250 MHz. Built-in LDOs deliver high PSRR performance and reduces the need for external ponents simplifying low jitter clock distribution in noisy environments. They are available in multiple configurations and offer a selectable input clock using a 2:1 input mux. Other features include independent output enable and built-in format translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance. KEY FEATURES - Ultra-low additive jitter: 50 fs rms - Built-in LDOs for high PSRR performance - Up to 10 LVDS Outputs - Any-format Inputs (LVPECL, Low-Power LVPECL, LVDS, CML, HCSL, LVCMOS) - Wide frequency range: dc to 1250 MHz - Output Enable option - Multiple configuration options - 2:1 Input Mux - Ro HS pliant, Pb-free - Temperature range: - 40 to +85 °C CLK0- CLK1- CLK_SEL Power Supply Filtering 03 3 4 Outputs Si53340/41 VDDOA OEAb 3 Outputs 3 Outputs OEBb VDDOB Si53342/43 10 10 Outputs Si53344/45 - Si53341/43/45 require Single-ended Inputs silabs. | Smart. Connected. Energy-friendly. Rev. 1.2 1. Ordering Guide Si53340-45 Data Sheet Ordering Guide Part Number SI53340-B-GM SI53341-B-GM SI53342-B-GM SI53343-B-GM SI53344-B-GM SI53345-B-GM Table 1.1. Si5334x Ordering Guide Input 2:1 selectable MUX Any-format 2:1 selectable MUX LVCMOS 2:1 selectable MUX Any-format 2:1 selectable MUX LVCMOS 2:1 selectable MUX Any-format 2:1 selectable MUX...