SI5347 Datasheet | Silicon Labs

Features - Four or two independent DSPLLs in a - Automatic free-run and holdover modes single monolithic IC - Fastlock feature for low nominal - Each DSPLL generates any output bandwidths frequency from any input frequency - Input frequency range: - Glitchless on-the-fly DSPLL frequency changes - Differential: 8 k Hz to 750 MHz - DCO mode: as low as 0.01 ppb steps - LVCMOS: 8 k Hz to 250 MHz - Output frequency range: per DSPLL - Core voltage: - Differential: up to 712.5 MHz - VDD: 1.8 V ±5% - LVCMOS: up to 250 MHz - Ultra low jitter: - VDDA: 3.3 V ±5% - Independent output clock supply pins: <100 fs typ (12 k Hz- 20 MHz) 3.3, 2.5, or 1.8 V - Flexible crosspoints route any input to - Output-output skew: any output clock - <20 ps (typ) per DSPLL - - Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz to 4 k Hz programming range Highly configurable outputs patible with LVDS, LVPECL, LVCMOS, CML, - - - Serial interface: I2C or SPI In-circuit programmable with non-volatile OTP memory Clock Builder TM Pro software tool and HCSL with programmable signal simplifies device configuration amplitude - Si5347: Quad DSPLL, 4 input, - Status monitoring (LOS, OOF, LOL) 4 or 8 output, 64 QFN - Hitless input clock switching: automatic - Si5346: Dual DSPLL, 4 input, or manual - Locks to gapped clock inputs 4 output, 44 QFN - Temperature range: - 40 to +85 °C - Pb-free, Ro HS-6 pliant Device Selector Guide Grade Si5347A Si5347C Si5346A Si5347B Si5347D Si5346B PLLs/OUTs 4/8 4/4 2/4 4/8 4/4...