Download the SI5347 datasheet PDF.
This datasheet also covers the SI5346 variant, as both devices belong to the same any-output jitter attenuators family and are provided as variant models within a single manufacturer datasheet.
General Description
The Si5347 is a high performance jitter attenuating clock multiplier which integrates four any-frequency DSPLLs for applications that require maximum integration and independent timing paths.
The Si5346 is a dual DSPLL version in a smaller package.
Key Features
Four or two independent DSPLLs in a.
Automatic free-run and holdover modes
single monolithic IC.
Fastlock feature for low nominal.
Each DSPLL generates any output
bandwidths
frequency from any input frequency.
Full PDF Text Transcription for SI5347 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
SI5347. For precise diagrams, and layout, please refer to the original PDF.
Si5347/46 D UAL/ Q UAD D S P L L A NY- F REQUENCY, A NY- O UTPUT J ITTER A TTENUATORS Si5347C/D Features Four or two independent DSPLLs in a Automatic free-run and ho...
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ures Four or two independent DSPLLs in a Automatic free-run and holdover modes single monolithic IC Fastlock feature for low nominal Each DSPLL generates any output bandwidths frequency from any input frequency Input frequency range: Glitchless on-the-fly DSPLL frequency changes Differential: 8 kHz to 750 MHz DCO mode: as low as 0.01 ppb steps LVCMOS: 8 kHz to 250 MHz Output frequency range: per DSPLL Core voltage: Differential: up to 712.5 MHz VDD: 1.8 V ±5% LVCMOS: up to 250 MHz Ultra low jitter: VDDA: 3.3 V ±5% Independent output clock supply pins: <100 fs typ (12 kHz–20 MHz) 3.3, 2.5,
SI5347 Datasheet
