Si5348 Datasheet | Silicon Labs

FEATURES - Three independent DSPLLs in a single monolithic IC supporting flexible Sync E/ IEEE 1588 and SETS architectures - Ultra-low jitter of 100 fs - Input frequency range: - External crystal: 48 to 54 MHz - REF clock: 5 to 250 MHz - Diff clock: 8 k Hz to 750 MHz - LVCMOS clock: 8 k Hz to 250 MHz - Output frequency range: - Differential: 1 PPS to 712.5 MHz - LVCMOS: 1 PPS to 250 MHz - Meets the requirements of: - ITU-T G.8273.2 T-BC - ITU-T G.8262 (Sync E) EEC Options 1 & - ITU-T G.812 Type III, IV - ITU-T G.813 Option 1 - Telcordia GR-1244, GR-253 (Stratum-3/3E) IN3 IN4 IN0 IN1 IN2 Status Flags I2C / SPI 48-54 MHz XTAL XA XB OSC TCXO/OCXO REFb REF ÷FRAC ÷FRAC ÷FRAC Status Monitor Control DSPLL D DSPLL C DSPLL A ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 Si5348 silabs. | Smart. Connected. Energy-friendly. Rev. 1.0 1. Feature List The Si5348 features are listed below: - Three independent DSPLLs in a single monolithic IC supporting flexible Sync E/IEEE 1588 and SETS architectures - Ultra-Low Jitter - 100 fs typ (12 k Hz to 20...