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Si5367
µP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Features
Not recommended for new
Five clock outputs with selectable
designs. For alternatives, see the signal format (LVPECL, LVDS,
Si533x family of products.
CML, CMOS)
Generates any frequency from Support for ITU G.709 FEC ratios
2 kHz to 945 MHz and select
(255/238, 255/237, 255/236)
frequencies to 1.4 GHz from an LOS alarm outputs
input frequency of 10 to 710 MHz Low jitter clock outputs w/jitter
generation as low as 0.6 ps rms
(50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth (150 kHz to 1.3 MHz)
Four clock inputs with manual or
automatically controlled
I2C or SPI programmable settings
On-chip voltage regulator for 1.8 V ±5%, 2.5 V ±10%, or 3.
Si5367 Datasheet
