SM502

SM502 Description

Initial Release  Updated clock frequency of SDRAM and 2D Engine  Updated description of PWM Interface  Updated the end address of 2D Engine Data Port (64-bit) in Figure 1-17  Updated the description of Current Clock Register, Power Mode 0 Clock Register and Power Mode 1 Clock Register: VIL and VIH in Table 18-2 DC Characteristics  Added new Table 18-3 I/O Drive Strength  Renumbered Table 18-4: 18-20  Added...