SST49LF020 Datasheet | Silicon Storage Technology

FEATURES : - Standard LPC Interface - Conforms to Intel LPC Interface Specification 1.0 - Organized as 256K x8 - Flexible Erase Capability - Uniform 4 KByte sectors - Uniform 16 KByte overlay blocks - 16 KBytes Top boot block protection - Chip-Erase for PP Mode - Single 3.0-3.6V Read and Write Operations - Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention - Low Power Consumption - Active Read Current: 10 m A (typical) - Standby Current: 10 µA (typical) - Fast Sector-Erase/Byte-Program Operation - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 µs (typical) - Chip Rewrite Time: 4 seconds (typical) - Single-pulse Program or Erase - Internal timing generation - Two Operational Modes - Low Pin Count (LPC) Interface mode for in-system operation - Parallel Programming (PP) Mode for fast production programming - LPC Interface Mode - 5-signal munication interface supporting byte Read and Write - 33 MHz clock frequency operation - WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block - Standard SDP mand Set - Data# Polling and Toggle Bit for End-of-Write detection - 5 GPI pins for system design flexibility - Parallel Programming (PP) Mode - 11 pin multiplexed address and 8 pin data I/O interface - Supports fast In-System or PROM programming for manufacturing - CMOS I/O patibility - Packages...