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monolithic dual n-channel JFETs
designed for • • •
• Very High Input Impedance DiHerential Amplifiers
Electrometers
• Impedance Converters
Performance Curves NNT See Section 4
BENEFITS
H
--Siliconix
• High Input Impedance
IG = 5 pA (U427) • High Gain 9fs = 120 Mmho Minimum @
10 = 30 MA
• Low Power Supply Operation
VGS(off} = 2 V Maximum (U427)
• Minimum System Error and Calibration
25 mV Maximum Offset
ABSOLUTE MAXIMUM RATINGS (25°C)
TO-78
Saa Section 6
Gate-to-Gate Voltage
Gate-Drain or Gate-Source Voltage
Gate Current
=Device Dissipation (Each Side), T A 25°C
±40V -40 V 10 mA
~~G, G2
(Derate 3.2 mW;oC to 150°C) .
400mW
8, 82
=Total Device Dissipation, T A 25° C
(Derate 6.
U427 Datasheet
