U630H64 Datasheet | Simtek

Features S High-performance CMOS nonvola S S S S S S S S S S S S Description The U630H64 has two separate modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U630H64 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through the state of the NE pin. The U630H64 bines the high performance and ease of use of a fast SRAM with nonvolatile data Pin Description integrity. Once a STORE cycle is initiated, further input or output are disabled until the cycle is pleted. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. S S tile static RAM 8192 x 8 bits 25, 35 and 45 ns Access Times 12, 20 and 25 ns Output Enable Access Times Hardware STORE Initiation (STORE Cycle Time < 10 ms) Automatic STORE Timing 105 STORE cycles to EEPROM 10 years data retention in EEPROM Automatic RECALL on Power Up Hardware RECALL Initiation (RECALL Cycle Time < 20 µs) Unlimited RECALL cycles from EEPROM Unlimited Read and Write to SRAM Single 5 V ± 10 % Operation Operating temperature ranges: 0 to 70 °C -40 to 85 °C QS 9000 Quality Standard ESD characterization according MIL STD 883C M3015.7-HBM (classification see IC Code Numbers) Ro HS pliance and Pb- free Packages: PDIP28 (300...