Si52204 Description
The Si52212, Si52208, and Si52204 can source twelve, eight, and four 100 MHz PCIe differential clock outputs, respectively, plus one 25 MHz LVCMOS reference clock output. The Si52202 can source two 100 MHz PCIe clock outputs only. All differential clock outputs are pliant to PCIe Gen1/2/3/4/5 mon clock and separate reference clock architectures specifications.
Si52204 Key Features
- Low jitter: 0.085 ps rms, Gen 6
- Individual hardware control pins and I2C controls
- Triangular spread spectrum for EMI reduction, down spread 0.25% or 0.5%
- Internal 100 Ω or 85 Ω line matching
- Adjustable output slew rate
- Power down (PWRDNb) function supports Wake-on LAN (except Si52202)
- One non-spread, LVMCOS reference clock output (except Si52202)
- Frequency Select to select 133 MHz or 200 MHz (except Si52202)
- 25 MHz crystal input or clock input
- I2C support with readback capabilities