Si53119-A03A Datasheet | Skyworks Solutions

Features - Nineteen 0.7 V low-power, push- - Integrated termination resistors pull HCSL PCIe Gen 3 outputs supporting 85  transmission - 100 MHz /133 MHz PLL lines operation, supports PCIe and - PLL or bypass mode - Spread spectrum tolerable - PLL bandwidth SW SMBUS - 1.05 to 3.3 V I/O supply voltage - - programming overrides the latch value from HW pin 9 selectable SMBUS addresses - - SMBus address configurable to - allow multiple buffers in a single control network 3.3 V supply 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) Low phase jitter (Intel® QPI, PCIe Gen 1/Gen 2/Gen 3 mon clock pliant) voltage operation - 100 ps input-to-output delay - Separate VDDIO for outputs - Gen3 SRNS pliant - Extended Temperature: - 40 to 85 °C - 72-pin QFN - For variations of this device, contact Skyworks Solutions Applications - Server - Storage - Data center - Enterprise switches and routers Description The Si53119-A03A is a 19-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. To reduce board space and bill of material cost, the device fully integrates all external resistors, supporting 85  transmission lines. It is optimized for distributing reference clocks for Intel® Quick Path Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Skyworks Solutions PCIe Clock Jitter Tool. Download it for free at https://.skyworksinc./en/application-pages/pci-express-learningcenter. Ordering Information: See page 31. Pin Assignments 72 DIF_18 71 DIF_18 70 GND 69 VDD_IO 68 DIF_17 67 DIF_17 66 DIF_16 65 DIF_16 64 VDD 63 GND 62 DIF_15 61 DIF_15 60 DIF_14 59 DIF_14 58...