Si5375 Datasheet | Skyworks Solutions

Features - Highly integrated, 4- PLL clock - Integrated loop filter with multiplier/jitter attenuator programmable bandwidth as low - Four independent DSPLLs as 60 Hz support any-frequency synthesis - Simultaneous free-run and and jitter attenuation synchronous operation - Four inputs/four outputs - Each DSPLL can generate any frequency from 2 k Hz to 808 MHz from a 2 k Hz to 710 MHz input - Automatic/manual hitless input clock switching - Selectable output clock signal format (LVPECL, LVDS, CML, CMOS) - Ultra-low jitter clock outputs: - LOL and interrupt alarm outputs 350 fs rms (12 k Hz- 20 MHz) - I2C programmable and 410 fs rms (50 k Hz- 80 MHz) typical - Single 1.8 V ±5% or 2.5 V ±10% operation with high PSRR on- - Meets ITU-T G.8251 and chip voltage regulator Telcordia GR-253-CORE OC-192 jitter specifications - 10x10 mm PBGA Applications - High density any-port, anyprotocol, any-frequency line cards - ITU-T G.709 OTN custom FEC - 10/40/100G - OC-48/192, STM-16/64 - 1/2/4/8/10G Fibre Channel - Gb E/10Gb E Synchronous Ethernet - Carrier Ethernet, multi-service switches and routers - MSPP, ROADM, P-OTS, muxponders Description The Si5375 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts an input clock ranging from 2 k Hz to 710 MHz and generates an output clock ranging from 2 k Hz to 808 MHz. The device provides virtually any frequency translation bination across this operating range. For asynchronous, free-running clock generation applications, the Si5375’s reference oscillator can be used as a clock source for any of the four DSPLLs. The Si5375 input clock frequency and clock multiplication ratio are programmable through an I2C interface. The Si5375 is based on Skyworks Solutions' third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly-integrated PLL solution...