Si5375 Datasheet PDF (4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR)

Si5375 - 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Description

The Si5375 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance.

Features

Highly integrated, 4.
PLL clock.
Integrated loop filter with multiplier/jitter attenuator programmable bandwidth as low.
Four independent DSPLLs as 60 Hz support any-frequency synthesis.
Simultaneous free-run and and jitter attenuation synchronous operation.
Four inputs/four outputs.
Each DSPLL can generate any frequency from 2 kHz to 808 MHz from a 2 kHz to 710 MHz input.
Automatic/manual hitless input clock switching.
Selectable output.

Datasheet Details

Part number	Si5375
Manufacturer	Skyworks
File Size	728.23 KB
Description	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Datasheet	Si5375 Datasheet
Additional preview pages of the Si5375 datasheet.

📁 Similar Datasheet

SI5375 - 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR (Silicon Laboratories)

SI5374 - 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR (Silicon Laboratories)

SI5376 - 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR (Silicon Laboratories)

SI530 - CRYSTAL OSCILLATOR (Silicon Laboratories)

SI53019-A01A - 19-OUTPUT PCIE GEN 3 BUFFER (Silicon Laboratories)

SI531 - CRYSTAL OSCILLATOR (Silicon Laboratories)

SI53102-A1 - FAN-OUT CLOCK BUFFER (Silicon Laboratories)

SI53102-A2 - FAN-OUT CLOCK BUFFER (Silicon Laboratories)

SI53102-A3 - FAN-OUT CLOCK BUFFER (Silicon Laboratories)

SI53106 - SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER (Silicon Laboratories)

Full PDF Text Transcription

Click to expand full text

Si5375 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features  Highly integrated, 4–PLL clock  Integrated loop filter with multiplier/jitter attenuator programmable bandwidth as low  Four independent DSPLLs as 60 Hz support any-frequency synthesis  Simultaneous free-run and and jitter attenuation synchronous operation  Four inputs/four outputs  Each DSPLL can generate any frequency from 2 kHz to 808 MHz from a 2 kHz to 710 MHz input  Automatic/manual hitless input clock switching  Selectable output clock signal format (LVPECL, LVDS, CML, CMOS)  Ultra-low jitter clock outputs:  LOL and interrupt alarm outputs 350 fs rms (12 kHz– 20 MHz)  I2C programmable and 410 fs rms (50 kHz–80 MHz) typical  Single 1.8 V ±5% or 2.

Published: Nov 13, 2023 |