Si5375 Description
The Si5375 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts an input clock ranging from 2 kHz to 710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. The device provides virtually any frequency translation bination across this operating range.
Si5375 Key Features
- Highly integrated, 4-PLL clock
- Four independent DSPLLs
- Simultaneous free-run and
- Four inputs/four outputs
- Each DSPLL can generate any frequency from 2 kHz to 808 MHz from a 2 kHz to 710 MHz input
- Automatic/manual hitless input clock switching
- Selectable output clock signal format (LVPECL, LVDS, CML, CMOS)
- Ultra-low jitter clock outputs
- LOL and interrupt alarm outputs
- I2C programmable