CXD3204R Datasheet | Sony Semiconductor Solutions

IEEE1394 LSI for D-STB, D-VHS, and DTV Description The CXD3204R is an LSI integrating Link Layer and Physical Layer conforming to the IEEE1394-1995 serial bus standard on a single chip. Link Layer provides MPEG2 transpor t stream dedicated input interface and output interface, IEC958 audio stream I/O interface and output interface for D/A c o nve r t e r a s a d a t a i n t e r fa c e fo i s o c h r o n o u s munication. Also, a maximum 512 bytes of asynchronous munication is possible. Physical Layer provides two poarts for 1394 cable i n t e r fa c e , a n d s u p p o r t s t r a n s fe r s p e e d o f 200/100Mbit/s. Also, this layer provides received packet data regeneration repeat function, arbitration function and bus initialization logic. T h i s L S I u t i l i ze s A p p l e C o m p u t e r ’s F i r e W i r e technology. 176-pin LQFP (Plastic) Feature Summary Ì Conforms to IEEE1394-1995 serial bus standard Ì Supports 100Mbps/200Mbps Ì Link layer x Supports DVB transport streams x Supports IEC958 audio stream x Built-in PID filter function x 2-channel isochronous simultaneous transmission/synchronous transmission and reception x Supports DMA (2-channel) transfer using host bus x Isochronous data inserted from asynchronous data port x Built-in cipher circuit conforming to DTCP format x Large capacity FIFO - Isochronous Transmit/Receive FIFO: 960 x 32-bit x 2 - Asynchronous Transmit FIFO: 132 x 33-bit - Asynchronous Receive FIFO: 133 x 33-bit x CIP header automatic attachment/detection Ì Physical layer x Live wire detection function when port is connected to operation node x Automatic shutdown function against stopport for powersaving x Bus initialization and arbitration state machine logic x Re-synchronization for reception data for local clock x Link-On packet recognition x DS link encode/decode x 196.603MHz PLL Ì Ì Ì Ì Ì Application Ì Digital interface for D-STB, D-VHS and DTV Absolute Max. Ratings (TA = 25o C, VSS = 0V) Supply...