P16M648YB7 Overview
The P16M648YA7 and P32M6416YA7 is a high performance dynamic random-access 256MB module, organized in a x64 configuration, and utilize quad bank architecture with a synchronous interface. All signals are registered on the positive edge of the clock signals CK0 through CK3. Read and write accesses to the SDRAM are burst oriented;.
P16M648YB7 Key Features
- PC-100 and PC133 patible
- Standard 168-pin , dual in-line memory
- TSOP ponents
- Single 3.3v +.3v power supply
- Nonbuffered fully synchronous; all signals measured
- Internal pipelined operation; column address can be changed every clock cycle
- Quad internal banks for hiding row access/precharge
- 64ms 4096 cycle refresh
- All inputs, outputs, clocks LVTTL patible
- 16Mx8 SDRAM TSOP 16