W196 Overview
CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by FS0:1 or the serial data interface. Output voltage swing is set by the voltage applied to VDDQ2.
W196 Key Features
- Maximized EMI suppression using Cypress’s Spread Spectrum Technology
- System frequency synthesizer for 440BX, 440ZX, and
- VDDQ2 = 2.5V±5% CPU Cycle to Cycle Jitter
- 250 ps CPU, PCI Output Edge Rate: t1 V/ns CPU0:1 Output Skew
- 175 ps PCI_F, PCI1:6 Output Skew
- 500 ps CPU to PCI Skew
- 1.5 to 4.0 ns (CPU Leads) REF2X/SEL48#, SCLOCK, SDATA
- 250-k: pull-up FS1
- 250-k: pull-down FS0
- I programmable to 155 MHz (32 selectable frequencies)
