DESCRIPTION
PIN CONFIGURATION (D-PAK) TO-252 TO-251 FEATURE 40V/20.0A, RDS(ON) = 13mΩ (Typ.) @VGS = 10V 40V/15.0A, RDS(ON) = 15mΩ @VGS = 4.5V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability TO-252,TO-251 package design PART MARKING Y: Year Code A: Week Code Q: Process Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA Copyright © 2009, Stanson Corp. STN4186D 2009. V1 STN4186D N Channel Enhancement Mode MOSFET 35.0A ABSOULTE MAXIMUM RATINGS
(Ta = 25℃ Unless otherwise noted ) Parameter Symbol Drain-Source Voltage VDSS Gate-Source Voltage VGSS Pulsed Drain Current IDM Continuous Source Current (Diode Conduction) Power Dissipation TA=25℃ TA=70℃ Operation Junction Temperature IS PD TJ Storgae Temperature Range TSTG Thermal Resistance-Junction to Ambient RθJA Typical 40 ±20 70 60 50 25 150 -55/150 60 Unit V V A A W ℃ ℃ ℃/W STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA Copyright © 2009, Stanson Corp.