DESCRIPTION
PIN CONFIGURATION SOP-8 FEATURE 40V/10.0A, RDS(ON) = 25mΩ @VGS = 10V 40V/8.0A, RDS(ON) = 31mΩ @VGS = 4.5V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOP-8 package design PART MARKING Y: Year Code A: Process Code B:Wafer Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA Copyright © 2007, Stanson Corp. STN45326 2007. V1 3 STN4536 Due N Channel Enhancement Mode MOSFET 10.0A ABSOULTE MAXIMUM RATINGS
(Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage VDSS 40 Gate-Source Voltage Continuous Drain Current (TJ=150℃) Pulsed Drain Current TA=25℃ TA=70℃ VGSS ID IDM ±20 10.0 8.0 30 Continuous Source Current (Diode Conduction) Power Dissipation TA=25℃ TA=70℃ Operation Junction Temperature IS PD TJ 2.3 2.5 1.6 150 Storgae Temperature Range TSTG -55/150 Thermal Resistance-Junction to Ambient RθJA 80 Unit V V A A A W ℃ ℃ ℃/W STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA Copyright © 2007, Stanson Corp.