STP2222ABGA Datasheet | Sun

STP2200ABGA July 1997 DATA SHEET DESCRIPTION The Uniprocessor System Controller (USC) has a DRAM memory controller and functions to regulate the flow of requests and data on the UPA bus. It also controls the resets going to all UPA clients. Uniprocessor System Controller Features - Controls up to eight standard SS-10/SS-20-type DRAM SIMMs - Supports various memory SIMM organizations: 16 MB, 64 MB, and 256 MB as well as dual-stacked 128-MB SIMMs - Controls and generates a number of resets for the system - Programmed via a standard 8-bit asynchronous interface (EBus) - JTAG interface allows full chip scan - 225-pin ABGA package Benefits - Standard workstation memory - Flexibility - High integration - Allows design of low-cost, low-chip-count embedded systems - Ease of design and testability - Low cost .. The USC is used as the system controller of a plete Uniprocessor Ultra SPARC system. Note: Instead of using the U2S, the USC can also be used with the UPA to PCI-bus; I/O interface controller (U2P) UPA Devices Abbreviations USC RIC U2S U2P XBI SC_UP RISC SYSIO Psycho BMX Part Number STP 2200ABGA STP2210QFP STP2220ABGA STP2222ABGA STP2230SOP Description Uniprocessor System Controller Reset/Interrupt/Clock Controller UPA to SBus I/O interface controller UPA to PCI bus I/O Interface controller Crossbar Data Path Note: This data sheet refers to the UPA to System I/O interface. The UPA to PCI bus Interface controller (U2P) can be substituted where U2S appears. STP2200ABGA USC Uniprocessor System Controller BLOCK AND TYPICAL APPLICATION DIAGRAMS Chip Boundary UPA_ADDRBUS0[34:0] UPA_ADR0_PAR0 UPA_ADDR0_VAL0[1:0] UPA_SC_REQ0 UPA_REQIN0[1:0] UPA_ADDRBUS1[28:0] UPA_ADDR1_VAL1 UPA_PREPLY0[4:0] UPA_PREPLY1[4:0] UPA_PREPLY2[4:0] BMX_CMD[3:0] x2 UPA_SREPLY0[4:0] UPA_SREPLY1[4:0] SYS_RESET X_BUTTON_RESET P_BUTTON_RESET UPA_RESET0 UPA_RESET1 UPA_XIR EBUS_CS EBUS_RD EBUS_WR EBUS_RDY EBUS_ADDR[2:0] EBUS_DATA[7:0] JTAG EBus Interface JTAG_TCK...