FEATURES
►► Processed with HVCMOS® technology ►► Sink current minimum 100mA ►► Shift register speed 8.0MHz ►► Polarity and Blanking inputs ►► CMOS compatible inputs ►► Forward and reverse shifting options ►► Diode to VPP allows efficient power recovery GENERAL DESCRIPTION
This device consists of a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. Data is shifted through the shift register on the high to low transition of the clock. The HV5630 shifts in the clockwise direction when viewed from the top of the package. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored when LE is low. Functional...