FEATURES
►►HVCMOS® technology ►►5.0V CMS Logic ►►Output voltage up to +80V ►►Low power level shifting ►►32MHz equivalent data rate ►►Latched data outputs ►►Foreward and reverse shifting options (DIR pin) ►►Diode to VPP allows efficient power recovery ►►Outputs may be hot switched GENERAL DESCRIPTION
The device has 4 parallel 16-bit registers, permitting data rates 4x the speed of one (they are clocked together). There are also 64 latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs.
Supertex Inc
