FEATURES
❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ HVCMOS® technology 5V CMOS inputs Up to 80V output voltage PWM gray shade conversion Capable of 256 levels of gray shading Balanced shift clock complies with RS-422 8MHz shift and count clock frequency 16MHz data throughput rate 8 bit data bus 32 outputs per device BLANK function GENERAL DESCRIPTION
Not recommended for new designs. Please use HV632 instead. Using Supertex’s unique HVCMOS® technology, it is capable of 256 levels of gray shading by PWM conversion. Input data, in groups of eight, is latched into a set of data latches on both edges of the shift clock. These data are compared to the contents of the master binary counter which counts on both edges of the count clock. Each time the master counter begins to decrement from 1111 1111, the data in the data latches are compared with the contents of the counter; if they match, the corresponding outputs will go high. The master counter counts down to 0000 0001 and then starts to count up again. The outputs that are at high will stay at high until the contents of the counter match the data in the data latches again.
Supertex Inc
