TN5325 - N-Channel Enhancement-Mode Vertical DMOS FETs

Supertex Inc

General Description

This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process.

Key Features

Low threshold (2.0V max. ).
High input impedance and high gain.
Free from secondary breakdown.
Low CISS and fast switching speeds.

📥 Download Datasheet

TN5325 n-channel enhancement-mode vertical dmos fets by Supertex Inc - Datasheet Preview

Datasheet Details

Part number	TN5325
Manufacturer	Supertex Inc
File Size	433.36 KB
Description	N-Channel Enhancement-Mode Vertical DMOS FETs
Datasheet	TN5325 Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
TN5325	N-Channel Vertical DMOS FET	Microchip
TN5015H-6G	High temperature 50A SCRs	STMicroelectronics
TN5015H-6I	High temperature 50A SCRs	STMicroelectronics
TN5015H-6T	High temperature 50A SCRs	STMicroelectronics
TN5050H-12WY	50A 1200V automotive grade thyristor	STMicroelectronics

Other Datasheets by Supertex Inc

Part Number	Description
TN5335	N-Channel Vertical DMOS FET

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

TN5325 N-Channel Enhancement-Mode Vertical DMOS FET Features ► Low threshold (2.0V max.) ► High input impedance and high gain ► Free from secondary breakdown ► Low CISS and fast switching speeds Applications ► Logic level interfaces - ideal for TTL and CMOS ► Solid state relays ► Battery operated systems ► Photo voltaic drives ► Analog switches ► General purpose line drivers ► Telecom switches General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefﬁcient inherent in MOS devices.