Datasheet4U Logo Datasheet4U.com

LS164 - 8-Bit Serial-Input/Parallel-Output Shift Register

Datasheet Summary

Features

  • gated serial inputs and an asynchronous reset. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip flop to the low level at the next clock pulse. A high level input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will b.

📥 Download Datasheet

Datasheet preview – LS164

Datasheet Details

Part number LS164
Manufacturer System Logic Semiconductor
File Size 36.46 KB
Description 8-Bit Serial-Input/Parallel-Output Shift Register
Datasheet download datasheet LS164 Datasheet
Additional preview pages of the LS164 datasheet.

📁 Similar Datasheet

  • LS1601-7R - 100 Watt AC-DC Converters (Power-One)
  • LS1691BM - FM/AM RADIO CIRCUIT (LIGHTNING Semiconductor)
  • LS10 - Surface mountable side-push switch (Citizen Electronics)
  • LS100 - Quad-Port Ethernet Switch Interface (I-CUBE)
  • LS1001-7R - 100 Watt AC-DC Converters (Power-One)
  • LS1008 - SMD Wire Wound Ferrite Chip Inductors (Chilisin Electronics)
  • LS101 - HIGH PERFORMANCE OPERATIONAL AMPLIFIERS (SGS)
  • LS101A - Small Signal Schottky Barrier Diodes (Vishay Siliconix)
  • LS101A-GS08 - Small Signal Schottky Barrier Diodes (Vishay Siliconix)
  • LS101A-GS18 - Small Signal Schottky Barrier Diodes (Vishay Siliconix)
Other Datasheets by System Logic Semiconductor
  • LS138 - 3-to-8-Line Decoder/Demultiplexer

Full PDF Text Transcription

Click to expand full text
SL74LS164 8-Bit Serial-Input/Parallel-Output Shift Register This 8-bit shift register features gated serial inputs and an asynchronous reset. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip flop to the low level at the next clock pulse. A high level input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will be entered clocking occurs or the low-to-high level transition of the clock input. All inputs are diodeclamped to minimize transmission-line effects.
Published: |