Datasheet Summary
SL74LV573 OCTAL D-TYPE TRANSPARENT LATCH (3-State)
By pinning SL74LV573 are patible with SL74HC573 and SL74HCT573 series. Input voltage levels are patible with stadard CMOS levels.
- Output voltage levels are patible with input levels of CMOS, NMOS and TTL ICS
- Voltage supply range from 1.2 to 5.5 V
- LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
- Output current 8 mÀ
- Latch current: not less than150 mÀ at Ò = 125 °Ñ
- ESD acceptable value: not less than 2000 V as per HBM and not less than 200 V as per MM
ORDERING INFORMATION SL74LV573N Plastic DIP SL74LV573D SOIC TA = -40° to 125° C for all packages
FUNCTION TABLE
Inputs OE L L L H LE H H L X D H L X X Outputs Q H L no...
