SL74HC112 Datasheet | System Logic Semiconductor

Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The SL74HC112 is identical in pinout to the LS/ALS112. The device inputs are patible with standard CMOS outputs; with pullup resistors, they are patible with LS/ALSTTL outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. - Outputs Directly Interface to CMOS, NMOS, and TTL - Operating Voltage Range: 2.0 to 6.0 V - Low Input Current: 1.0 µA - High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC112N Plastic SL74HC112D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Set L H L H H H...