SL74HC165 Datasheet | System Logic Semiconductor

8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS The SL74HC165 is identical in pinout to the LS/ALS165. The device inputs are patible with standard CMOS outputs; with pullup resistors, they are patible with LS/ALSTTL outputs. This device is an 8-bit shift register with plementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/ Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2 -input NOR clock may be used either by bining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. - Outputs Directly Interface to CMOS, NMOS, and TTL - Operating Voltage Range: 2.0 to 6.0 V - Low Input Current: 1.0 µA - High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC165N Plastic SL74HC165D SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 16=VCC PIN 8 = GND FUNCTION TABLE Inputs Serial Shift/ Parallel Load L H H H H H H H L L X H L H X L Clock H Clock Inhibit X L L SA X L H L H X X X A-H a...h X X X X X X X no change No Clock Internal Stages QA a L H L H QB-QG b-g QAn-QFn QAn-QFn QAn-QFn QAn-QFn no change Output QH h QGn QGn QGn QGn Serial Shift via Clock Inhibit Inhibited Clock Asynchronous Parallel Load Serial Shift via Clock Operation X = Don’t Care QAn-QFn = Data shifted from the preceding stage System Logic Semiconductor MAXIMUM RATINGS - Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL - Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC...