SL74HC174
SL74HC174 is Hex D Flip-Flop with Common Clock and Reset manufactured by System Logic Semiconductor.
Hex D Flip-Flop with mon Clock and Reset
High-Performance Silicon-Gate CMOS
The SL74HC174 is identical in pinout to the LS/ALS174. The device inputs are patible with standard CMOS outputs; with pullup resistors, they are patible with LS/ALSTTL outputs. This device consists of six D flip-flops with mon Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active-low.
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 µA
- High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION SL74HC174N Plastic SL74HC174D SOIC TA = -55° to 125° C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
Inputs Reset L PIN 16=VCC PIN 8 = GND H H H H X = Don’t care L Clock X D X H L X X Output Q L H L no change no change
System Logic Semiconductor
MAXIMUM RATINGS
- Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
- Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260
Unit V V V m A m A m A m W °C °C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Remended Operating Conditions. +Derating
- Plastic DIP:
- 10 m W/°C from 65° to 125°C SOIC Package: :
- 7 m W/°C from 65° to 125°C
REMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)...