SL74LV138 Datasheet | System Logic Semiconductor

3-TO-8 DECODER/DEMULTIPLEXER By pinning SL74LV138 are patible with SL74HC138 and SL74HCT138 series. Input voltage levels are patible with standard CMOS ones. - Output voltage levels are patible with input levels of CMOS, NMOS and TTL ICS - Supply voltage range is from 1.2 to 5.5 V - Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ - Output current 6 mÀ - Latch current is not less than 150 mÀ at Ò = 125 °Ñ - ESD acceptable values: than 2000 V as per HBM, and not less than 200 V as per MM BLOCK DIAGRAM Y0 ORDERING INFORMATION SL74LV138N Plastic DIP SL74LV138D SOIC TA = -40° to 125° C for all packages Y1 PIN ASSIGNMENT A0 A1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q0...