FEATURES
D Power control modes D 256 bytes of RAM D 8 Kbytes of ROM (80C52) D 32 programmable I/O lines D Three 16 bit timer/counters D 64 K program memory space D 64 K data memory space D Fully static design D 0.8µ CMOS process D Boolean processor D 6 interrupt sources D Programmable serial port D Temperature range : commercial, industrial, automotive, military Optional D Secret ROM : Encryption D Secret TAG : Identification number MATRA MHS Rev. G (14 Jan. 97) 1 80C32/80C52 Interface Figure 1. Block Diagram 2 MATRA MHS Rev. G (14 Jan. 97) Figure 2. Pin Configuration 80C32/80C52 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 NC VCC P0.0/A0 P0.1/A1 P0.2/A2 P0.3/A3 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 80C32/80C52 P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA NC ALE PSEN P2.7/A14 P2.6/A13 P2.5/A12 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS NC P2.0/A7 P2.1/A8 P2.2/A9 P2.3/A10 P2.4/A11 DIL P15 P16 P17 RST RxD/P30 NC TxD/P31 INT0/P32 INT1/P33 T0/P34 T1/P35 P14 P13 P12 P11/T2EX P10 /T2 NC...
TEMIC Semiconductors
