Description
No Connection Data bit0 Data bit1 Data bit2 Data bit3 Data bit4 Data bit5 Data bit6 Data bit7 Reset signal input Chip select input Selects registers, L:Control data, H:Display data Write Signal Read Signal Ground Power supply voltage for logic No Connection No Connection 8/21 Ver. 1.0 6.3 Interface Timing Chart CD tAS80 CS0, CS1 tAH80 tCY80 tPWR80, tPWW80 tHPW80 WR0, WR1 0.8VDD 0.2VDD tDS80 D[7:0] Write tDH80 tACC80 D[7:0] Read tOD80 Figure 21: Parallel Bus Timing Characteristics (for 8080 MCU) o (VDD=2.4V to 3.0V, Ta= –30 to +85 C) Symbol tAS80 tAH80 tCY80 tPWR80 tPWW80 tHPW80 tDS80 tDH80 tACC80 tOD80 Signal CD Description Address setup time Address hold time System cycle time Pulse width (read) Pulse width (write) High pulse width Data setup time Data hold time Read access time Output disable time Condition Min.
