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UG01 - 0.6um ULC

This page provides the datasheet information for the UG01, a member of the UG09 0.6um ULC family.

Datasheet Summary

Description

The UG series of ULCs is well suited for conversion of medium- to-large sized CPLDs and FPGAs.

Features

  • D High performance ULC family suitable for medium- to large-sized CPLDs and FPGAs D Conversions to over 200,000 FPGA gates D Pin counts to over 300 pins D Any pin-out matched due to limited number of dedicated pads D Advanced 0.6-µm (drawn)/0.45-µm (effective) feature size D Triple-layer or dual-layer metal CMOS technology D High speed performance:.
  • 250-ps typical cell delay.
  • 350-MHz toggle rate D Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, PGA/PPGA D 3.3V and/or 5.

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Datasheet preview – UG01

Datasheet Details

Part number UG01
Manufacturer Temic
File Size 85.13 KB
Description 0.6um ULC
Datasheet download datasheet UG01 Datasheet
Additional preview pages of the UG01 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com UG Series 0.6µm ULC Series Description The UG series of ULCs is well suited for conversion of medium- to-large sized CPLDs and FPGAs. Devices are implemented in high-performance CMOS technology with 0.6-µm (drawn) channel lengths, and are capable of supporting flip-flop toggle rates of 350 MHz, operating clock frequencies up to 150 MHz and input to output delays as fast as 5 ns. The architecture of the UG series allows for efficient conversion of many PLD architectures and FPGA device types. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary-scan and scan-path testing.
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