TM58P20 Datasheet | Tenx

Feature ROM: 2K x 14 bits RAM: 96 x 8 bits STACK: 4 Levels I/O ports: 20 I/O PAD Timer/counter: 8bits x1 (TMR0) Prescaler: 8 Bits Two IRQ sources: Internal IRQ: (TMR0) External IRQ: (PA0) Watchdog Timer: On chip WDT is based on internal RC oscillator. The shortest period is 20m S; user can extend the WDT overflow period to 2.6S by using prescaler. Power-On Reset & Power-Down Reset Reset Timer: 20 m S (5V) Four external Oscillate modes: RC,LP Crystal,NT Crystal and HS Crystal. Two operation modes: General mode, and Advanced mode Operation Voltage: 2.2V¡ã 5.5V Instruction set: 79 Wake-up: Watchdog timer overflow, Port A (PA3~ PA0) Reset vector: 7FFH IRQ vector: 7FEH Low voltage reset: voltage shortage will result in reset 1 tenx technology, inc. Rev1.2 2004/3/5 .. 2. Pin Definition & Pad Assignment RTCC VDD NC VSS NC PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RESETB/VPP OSC1 OSC2 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 Package Types of 28Pin: DIP, SOP. RESETB/VPP RTCC VDD VSS PA0 PA1 PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OSC1 OSC2 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 Package Types of 20Pin: DIP, SOP. 2 tenx technology, inc. Rev1.2 2004/3/5 .. PIN description Pin name RTCC PA0 PA3-1 PB7-0 PC7-0 RESETB/VPP OSC1 OSC2 VDD VSS I/O I I/O I/O I/O I/O I I O P P Description External clock input to TMR0 counter I/O port & External IRQ input & wake-up input I/O port & wake-up (input mode) I/O port I/O port System reset signal & VPP (High voltage) input 1 Low voltage: reset mode 2 High voltage: programming mode Oscillator input Oscillator output Power input Ground input I: Input; O: Output; I/O: Bi-direction; P: Power 3. Control Register Name CONFIG (Instruction) SELECT IAR TMR0 PC STATUS BSR I/O Port A I/O Port B I/O Port C WAKE_UP IRQM IRQF Addr Bit 7 Bit 6 LV1 Bit 5 LV0 Bit 4 Bit 3 Bit 2 WDTE PS2 A2 D2 D2 Z D2 PA2 PB2 PC2 PUH2 EXINTM EXINTF Bit 1 Bit 0 TYPE...