74HC02AP Overview
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The internal circuit is posed of 3 stages, including a buffer output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage.
74HC02AP Key Features
- High speed: tpd = 6 ns (typ.) at VCC = 5 V Low power dissipation: ICC = 1 μA (max) at Ta = 25°C High noise immunity: VNI
- Wide operating voltage range: VCC (opr) = 2~6 V Pin and function patible with 74LS02
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