Datasheet4U Logo Datasheet4U.com

TC55V16256FTI-15 - MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Download the TC55V16256FTI-15 datasheet PDF. This datasheet also covers the TC55V16256FTI-12 variant, as both devices belong to the same mos digital integrated circuit silicon gate cmos family and are provided as variant models within a single manufacturer datasheet.

General Description

The TC55V16256JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144 words by 16 bits.

Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply.

Key Features

  • Fast access time (the following are maximum values) TC55V16256JI/FTI-12:12 ns TC55V16256JI/FTI-15:15 ns Low-power dissipation (the following are maximum values) Cycle Time Operation (max) 12 230 15 200 20 170 25 150 ns mA.
  • Standby:10 mA (both devices) Single power supply voltage of 3.3 V ± 0.3 V Fully static operation All inputs and outputs are LVTTL compatible Output buffer control using OE Data byte control usin.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC55V16256FTI-12_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TC55V16256FTI-15
Manufacturer Toshiba
File Size 223.48 KB
Description MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Datasheet download datasheet TC55V16256FTI-15 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC55V16256JI/FTI-12,-15 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION The TC55V16256JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide lower and upper byte access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible.