TC59LM906AMG-37 Datasheet | Toshiba

Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle Random Access Memory (Network FCRAMTM) containing 536,870,912 memory cells. TC59LM914AMG is organized as 4,194,304-words × 8 banks × 16 bits, TC59LM906AMG is organized as 8,388,608-words × 8 banks × 8 bits. TC59LM914/06AMG feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM914/06AMG can operate fast core cycle pared with regular DDR SDRAM. TC59LM914/06AMG is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition. Features PARAMETER CL = 3 t CK Clock Cycle Time (min) CL = 4 CL = 5 t RC Random Read/Write Cycle Time (min) t RAC Random Access Time (max) IDD1S Operating Current (single bank) (max) l DD2P Power Down Current (max) l DD6 Self-Refresh Current (max) TC59LM914/06 -37 5.5 ns 4.5 ns 3.75 ns 22.5 ns 22.0 ns 280 m A 90 m A 20 m A -50 6.0 ns 5.5 ns 5.0 ns 27.5 ns 24.0 ns 240 m A 80 m A 20 m A - - - - - - - - - - - - - - - - Fully Synchronous Operation - Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS. - Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and DQS) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.75 ns minimum Clock: 266 MHz maximum Data: 533 Mbps/pin maximum Fast cycle and Short Latency Eight independent banks operation When BA2 input assign to A14 input, TC59LM914/06AMG can function as 4 bank device (Keep backward patibility to 256Mb) Bidirectional differential data strobe signal : TC59LM906AMG Bidirectional data strobe signal per byte : TC59LM914AMG Distributed Auto-Refresh cycle in 3.9 µs...