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TC74AC367F - Hex Bus Buffer

Download the TC74AC367F datasheet PDF. This datasheet also covers the TC74AC367P variant, as both devices belong to the same hex bus buffer family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: tpd = 3.7 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 5.5 V.
  • Pin and function compatible with 74F367 TC74AC367P TC74AC367F TC74AC367FT W.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74AC367P_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
TC74AC367FN Hex Bus Buffer Toshiba
TC74AC367FT Hex Bus Buffer Toshiba
TC74AC373FT Octal D-Type Latch Toshiba
TC74AC373FW Octal D-Type Latch Toshiba
TC74AC374FT Octal D-Type Flip-Flop Toshiba

Other Datasheets by Toshiba

Part Number Description
TC74AC367P Hex Bus Buffer
TC74AC32F Quad 2-Input OR Gate
TC74AC32FN Quad 2-Input OR Gate
TC74AC32FT Quad 2-Input OR Gate
TC74AC32P Quad 2-Input OR Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74AC367P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC367P, TC74AC367F, TC74AC367FT Hex Bus Buffer (3-state) The TC74AC367 is an advanced high speed CMOS HEX BUS BUFFERs fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It contains six buffers; four buffers are controlled by an enable input ( G1 ), and the other two buffers are controlled by another enable input ( G2 ). The outputs of each buffer group are enabled when G1 and/or G2 inputs are held low; if held high, these outputs are in a high impedance state.