Datasheet4U Logo Datasheet4U.com

TC74AC373P - Octal D-Type Latch

Download the TC74AC373P datasheet PDF. This datasheet also covers the TC74AC373F variant, as both devices belong to the same octal d-type latch family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: tpd = 4.8 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 5.5 V.
  • Pin and function compatible with 74F373 TC74AC373P TC74AC373F TC74AC373FT W.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74AC373F_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
TC74AC373FT Octal D-Type Latch Toshiba
TC74AC373FW Octal D-Type Latch Toshiba
TC74AC374FT Octal D-Type Flip-Flop Toshiba
TC74AC374FW OCTAL D-TYPE FLIP-FLOP Toshiba
TC74AC367FN Hex Bus Buffer Toshiba

Other Datasheets by Toshiba

Part Number Description
TC74AC373F Octal D-Type Latch
TC74AC374F Octal D-Type Flip-Flop
TC74AC374P Octal D-Type Flip-Flop
TC74AC377F Octal D-Type Flip-Flop
TC74AC377FW OCTAL D-TYPE FLIP-FLOP

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74AC373P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC373P, TC74AC373F, TC74AC373FT Octal D-Type Latch with 3-State Output The TC74AC373 is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. These 8-bit D-type latches are controlled by a latch enable input (LE) and a output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 4.8 ns (typ.