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TC74AC74FN - DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

Download the TC74AC74FN datasheet PDF. This datasheet also covers the TC74AC74F variant, as both devices belong to the same dual d type flip flop with preset and clear family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: fmax = 200 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 V to 5.5 V.
  • Pin and function compatible with 74F74 Note: xxxFN (JEDEC SOP) is not av.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74AC74F_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TC74AC74FN
Manufacturer Toshiba
File Size 268.58 KB
Description DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
Datasheet download datasheet TC74AC74FN Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
TC74AC74F Dual D-Type Flip-Flop Toshiba
TC74AC74FT Dual D-Type Flip-Flop Toshiba
TC74AC74P Dual D-Type Flip-Flop Toshiba
TC74AC00F Quad 2-Input NAND Gate Toshiba
TC74AC00FT Quad 2-Input NAND Gate Toshiba

Other Datasheets by Toshiba

Part Number Description
TC74AC00FN QUAD 2 - INPUT NAND GATE
TC74AC02F Quad 2-Input NOR Gate
TC74AC02P Quad 2-Input NOR Gate
TC74AC04F HEX INVERTER
TC74AC04P HEX INVERTER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74AC74P/F/FN/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC74P,TC74AC74F,TC74AC74FN,TC74AC74FT Dual D-Type Flip Flop with Preset and Clear The TC74AC74 is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an “L” level. All inputs are equipped with protection circuits against static discharge or transient excess voltage.