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TC74ACT175FN - Quad D-Type Flip Flop with Clear

Download the TC74ACT175FN datasheet PDF. This datasheet also covers the TC74ACT175F variant, as both devices belong to the same quad d-type flip flop with clear family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: fmax = 160 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C.
  • Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Pin and function compatible with 74F175 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74ACT175P TC7.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74ACT175F_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TC74ACT175FN
Manufacturer Toshiba
File Size 282.99 KB
Description Quad D-Type Flip Flop with Clear
Datasheet download datasheet TC74ACT175FN Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC74ACT175F Quad D-Type Flip-Flop
TC74ACT175P Quad D-Type Flip-Flop
TC74ACT138F 3-to-8 Line Decoder
TC74ACT138FN 3 - TO - 8 LINE DECODER
TC74ACT138FS 3 - TO - 8 LINE DECODER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74ACT175P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT175P,TC74ACT175F,TC74ACT175FN Quad D-Type Flip Flop with Clear The TC74ACT175 is an advanced high speed CMOS QUAD D-TYPE FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. These four flip-flops are controlled by a clock input (CK) and a clear input ( CLR ).