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TC74ACT273FW - Octal D-Type Flip Flop with Clear

Download the TC74ACT273FW datasheet PDF. This datasheet also covers the TC74ACT273F variant, as both devices belong to the same octal d-type flip flop with clear family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: fmax = 170 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C.
  • Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Pin and function compatible with 74F273 Pin Assignment Note: xxxFW (JEDEC SOP) is not available in Japan. TC74ACT273P TC7.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74ACT273F_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TC74ACT273FW
Manufacturer Toshiba
File Size 246.97 KB
Description Octal D-Type Flip Flop with Clear
Datasheet download datasheet TC74ACT273FW Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC74ACT273F Octal D-Type Flip-Flop
TC74ACT273P Octal D-Type Flip-Flop
TC74ACT240F Octal Bus Buffer
TC74ACT240FT Octal Bus Buffer
TC74ACT240FW OCTAL BUS BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74ACT273P/F/FW TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT273P,TC74ACT273F,TC74ACT273FW Octal D-Type Flip Flop with Clear The TC74ACT273 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse.