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TC74HC112AF - Dual J-K Flip Flop

Key Features

  • High speed: fmax = 67 MHz (typ. ) at VCC = 5 V Low power dissipation: ICC = 2 μA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Output drive capability: 10 LSTTL loads Symmetrical output impedance: |IOH| = IOL = 4 mA (min) ∼ tpHL Balanced propagation delays: tpLH.
  • Wide operating voltage range: VCC (opr) = 2 to 6 V Pin and function compatible with 74LS112 TC74HC112AFN Pin Assignment Wei.

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Other Datasheets by Toshiba

Part Number Description
TC74HC112AFN Dual J-K Flip-Flop
TC74HC112AP Dual J-K Flip-Flop
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet.co.kr TC74HC112AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC112AP,TC74HC112AF,TC74HC112AFN Dual J-K Flip Flop with Preset and Clear The TC74HC112A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to the J and K inputs, the outputs change state on the negative going transition of the clock pulse. CLR and PR are independent of the clock and are actived by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Note: xxxFN (JEDEC SOP) is not available in Japan.